This invention relates to integrated optical circuit fabrication, and more particularly to a novel process for fabrication of optical waveguides, whereby lift-off, rather than etching, is used to pattern the waveguide core.
Products based on so-called planar lightwave circuits (PLCs) have the possibility of significantly reducing the cost and size of optical components, while at the same time enhancing functionality. Notable in this area is the work on doped SiO2 glass (See, e.g., M. Kawachi, Optical and Quantum Electronics 22 (1990) 391-416). These low-doped glassy waveguide structures are similar to well-known silica optical fibers with respect to optical guiding and hence have similar modal fields resulting in low coupling losses between the chip and standard single mode fiber.
However, an inherent disadvantage of these low-index-contrast glassy structures is a rather large minimum radius of curvature allowable in circuits, typically greater than 15 mm. Devices containing many bends become very large, such that only a small number of them may be arranged on a wafer, which is less cost-effective. In order to fabricate optical components in a more cost-effective way in mass production, it is desirable to increase the device density.
FIG. 1a to FIG. 1h illustrates schematically the steps in an exemplary conventional process for manufacturing channel waveguides 10. As illustrated in FIG. 1a, a silicon substrate 12 is first provided and a lower cladding layer 14 is deposited on its upper surface. Referring to FIG. 1b, a core layer 16 is deposited on top of the cladding layer. The cladding layer 14 and core layer 16 may be deposited by various methods, such as flame hydrolysis deposition (FHD), chemical vapor deposition (CVD), plasma-enhanced CVD (PECVD), sol-gel, etc. An example for high index contrast material for fabrication of planar waveguides may be found in PCT publication WO 99/54714, where SiON and SiO2 are used as a core and cladding layers, respectively.
An alternative embodiment includes a lower optical cladding comprising a substrate of a transparent material having an appropriate index, such as a Ge doped SiO2 core on an undoped fused quartz substrate.
In the next step (FIG. 1c), the core layer 16 is annealed. Following core layer annealing (FIG. 1d), a photoresist or metal mask 18 is coated over the core layer 16. Photolithography (FIG. 1e) and reactive ion etching (RIE) (FIG. 1f) are used to define the desired ridge structure. The photoresist or metal mask 18 is stripped as illustrated in FIG. 1g. Finally, FIG. 1h illustrates deposition of an upper cladding layer 20.
As seen in FIG. 1a to FIG. 1h conventional etching processes require a large number of steps. RIE in particular is a time-consuming step in processing. RIE also may produce wall roughness that may lead to scattering loss in the resulting channel waveguide. Additionally, conventional methods require significant capital investment to provide necessary equipment and processes.
Given the difficulties with traditional etching, other methods used in integrated circuit manufacturing have been attempted. However, there have been difficulties, such as tearing or damage, applying these methods to the fabrication of optical waveguides.
The desire remains for a more efficient and cost-effective method for fabrication of optical waveguides.